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    제목(국문) Mechanism for mitigating filler-induced reliability degradation in semiconductor devices assembled utilizing an LOC package technique
    제목(영문)
    저자 (Seong-Min Lee ,Department of Materials Science and Engineering, University of Incheon ) ▷공저자네트워크등록하기
    (Yeon-Wook Kim ,Department of Materials Science and Engineering, Keimyung University ) ▷공저자네트워크등록하기
    초록
    초록(영문)

    This work illustrates a mechanism for mitigating filler-induced reliability degradation in semiconductor devices assembled utilizing an LOC (lead-on-chip) package technique. Based on the mechanism, this article provides two fundamental solutions to solve the filler-driven problem in semiconductor products. First of all, in order to avoid filler-driven pattern damage during thermal-cycling, the maximum filler size in the plastic package body should have a diameter smaller than half of the inter-distance between the device pattern and it’s overlying lead-frame. Second, for effective prevention of filler-induced failure, the minimum distance between the polyimide coverage and each pad should be maintained to have a dimension that corresponds to the polyimide thickness. This article conclusively shows that the proper combination of two solutions can allow semiconductor products to have better reliability margins in use.

    keyword Silicon wafer, Chip, Reliability, Semiconductor
    저널명 Journal of Mechanical Science and Technology ▷관련저널보기
    VOL 34
    PAGE 0675
    발표년도 2020
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