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기술보고서

기술보고서 게시판 내용
타이틀	Digital Synchronizer without Metastability
저자	Simle, Robert M.;; Cavazos, Jose A.
Keyword	DIGITAL ELECTRONICS;; SYNCHRONIZERS;; METASTABLE STATE;; LOGIC CIRCUITS;; CLOCKS;; PULSE DURATION;; DISCRIMINATORS;; FAILURE;;
URL	http://hdl.handle.net/2060/20090032096
보고서번호	MSC-23220-1
발행년도	2009
출처	NTRS (NASA Technical Report Server)
ABSTRACT	A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for Ƒ) use of a clock frequency greater than the frequency of the asynchronous signal, ƒ) use of flip-flop asynchronous preset or clear signals for the asynchronous input, Ɠ) use of a clock asynchronous recovery delay with pulse width discriminator, and Ɣ) tying the data inputs to constant logic levels to obtain ƕ) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.